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sycl: Use syclcompat::dp4a (#10267)
* sycl: Use syclcompat::dp4a
* Using the syclcompat version allow the compiler to optimize the
operation with native function
* Update news section
* Update CI Windows oneAPI version to 2025.0
* Reword doc
* Call syclcompat::dp4a inside dpct::dp4a
This reverts commit 90cb61d692
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.github/workflows/build.yml
vendored
2
.github/workflows/build.yml
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@ -930,7 +930,7 @@ jobs:
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shell: bash
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shell: bash
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env:
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env:
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WINDOWS_BASEKIT_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/7dff44ba-e3af-4448-841c-0d616c8da6e7/w_BaseKit_p_2024.1.0.595_offline.exe
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WINDOWS_BASEKIT_URL: https://registrationcenter-download.intel.com/akdlm/IRC_NAS/b380d914-366b-4b77-a74a-05e3c38b3514/intel-oneapi-base-toolkit-2025.0.0.882_offline.exe
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WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel
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WINDOWS_DPCPP_MKL: intel.oneapi.win.cpp-dpcpp-common:intel.oneapi.win.mkl.devel
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ONEAPI_ROOT: "C:/Program Files (x86)/Intel/oneAPI"
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ONEAPI_ROOT: "C:/Program Files (x86)/Intel/oneAPI"
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steps:
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steps:
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@ -41,6 +41,8 @@ The following release is verified with good quality:
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## News
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## News
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- 2024.11
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- Use syclcompat to improve the performance on some platforms. This requires to use oneAPI 2025.0 or newer.
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- 2024.8
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- 2024.8
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- Use oneDNN as the default GEMM library, improve the compatibility for new Intel GPUs.
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- Use oneDNN as the default GEMM library, improve the compatibility for new Intel GPUs.
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@ -15,6 +15,7 @@
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#include <sycl/sycl.hpp>
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#include <sycl/sycl.hpp>
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#include <sycl/half_type.hpp>
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#include <sycl/half_type.hpp>
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#include <syclcompat/math.hpp>
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#include <oneapi/mkl.hpp>
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#include <oneapi/mkl.hpp>
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#include <map>
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#include <map>
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@ -1830,31 +1831,10 @@ namespace dpct
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: id);
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: id);
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}
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}
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template <typename T>
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sycl::vec<T, 4> extract_and_sign_or_zero_extend4(T val)
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{
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return sycl::vec<T, 1>(val)
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.template as<sycl::vec<
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std::conditional_t<std::is_signed_v<T>, int8_t, uint8_t>, 4>>()
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.template convert<T>();
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}
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template <typename T1, typename T2>
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using dot_product_acc_t =
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std::conditional_t<std::is_unsigned_v<T1> && std::is_unsigned_v<T2>,
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uint32_t, int32_t>;
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template <typename T1, typename T2, typename T3>
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template <typename T1, typename T2, typename T3>
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inline auto dp4a(T1 a, T2 b, T3 c)
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inline auto dp4a(T1 a, T2 b, T3 c)
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{
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{
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dot_product_acc_t<T1, T2> res = c;
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return syclcompat::dp4a(a, b, c);
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auto va = extract_and_sign_or_zero_extend4(a);
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auto vb = extract_and_sign_or_zero_extend4(b);
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res += va[0] * vb[0];
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res += va[1] * vb[1];
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res += va[2] * vb[2];
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res += va[3] * vb[3];
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return res;
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}
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}
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struct sub_sat
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struct sub_sat
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@ -968,8 +968,8 @@ vec_dot_iq3_xxs_q8_1(const void *__restrict__ vbq,
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grid1[0] ^ signs[0], signs[0], std::minus<>());
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grid1[0] ^ signs[0], signs[0], std::minus<>());
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const int grid_h = dpct::vectorized_binary<sycl::uchar4>(
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const int grid_h = dpct::vectorized_binary<sycl::uchar4>(
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grid2[0] ^ signs[1], signs[1], std::minus<>());
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grid2[0] ^ signs[1], signs[1], std::minus<>());
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sumi = dpct::dp4a(grid_l, *((int *)q8 + 0), sumi);
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sumi = dpct::dp4a(grid_l, *((const int *)q8 + 0), sumi);
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sumi = dpct::dp4a(grid_h, *((int *)q8 + 1), sumi);
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sumi = dpct::dp4a(grid_h, *((const int *)q8 + 1), sumi);
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q8 += 8;
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q8 += 8;
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aux32 >>= 7;
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aux32 >>= 7;
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}
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}
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@ -1009,8 +1009,8 @@ vec_dot_iq3_s_q8_1(const void *__restrict__ vbq,
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grid1[0] ^ signs0, signs0, std::minus<>());
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grid1[0] ^ signs0, signs0, std::minus<>());
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const int grid_h = dpct::vectorized_binary<sycl::uchar4>(
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const int grid_h = dpct::vectorized_binary<sycl::uchar4>(
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grid2[0] ^ signs1, signs1, std::minus<>());
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grid2[0] ^ signs1, signs1, std::minus<>());
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sumi = dpct::dp4a(grid_l, *((int *)q8 + 0), sumi);
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sumi = dpct::dp4a(grid_l, *((const int *)q8 + 0), sumi);
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sumi = dpct::dp4a(grid_h, *((int *)q8 + 1), sumi);
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sumi = dpct::dp4a(grid_h, *((const int *)q8 + 1), sumi);
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q8 += 8;
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q8 += 8;
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}
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}
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const float d =
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const float d =
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