mirror of
https://github.com/ggerganov/llama.cpp.git
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ggml : vector length agnostic SVE support (#9290)
* Implemented vector length agnostic SVE using switch case for 512-bit, 256-bit, 128-bit vector lengths * Implemented vector length agnostic SVE using switch case for 512-bit, 256-bit, 128-bit vector lengths * Removed WhiteSpaces * ggml : style changes + fix 512-bit nb loop check - fix local scope in switch cases - consistent predicate names - empty lines when necessary - opening braces, spaces - const-correctness - add asserts * Update ggml/src/ggml-quants.c Co-authored-by: Georgi Gerganov <ggerganov@gmail.com> --------- Co-authored-by: Georgi Gerganov <ggerganov@gmail.com>
This commit is contained in:
Prashant Vithule
GitHub
parent
5fb5e24811
commit
5fac4d5764
@ -4003,13 +4003,18 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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float sumf = 0;
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#if defined(__ARM_FEATURE_SVE)
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if (ggml_sve_cnt_b == QK8_0) {
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const svbool_t ptrueh = svptrue_pat_b8(SV_VL16);
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const svbool_t ptruel = svnot_b_z(svptrue_b8(), ptrueh);
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svfloat32_t sumv0 = svdup_n_f32(0.0f);
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svfloat32_t sumv1 = svdup_n_f32(0.0f);
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const int vector_length = ggml_sve_cnt_b*8;
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// VLA Implementation using switch case
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switch (vector_length) {
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case 128:
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{
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// predicate for activating higher lanes for 4 float32 elements
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const svbool_t ph4 = svptrue_pat_b32(SV_VL4);
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for (; ib + 1 < nb; ib += 2) {
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const block_q4_0 * restrict x0 = &x[ib + 0];
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const block_q4_0 * restrict x1 = &x[ib + 1];
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@ -4021,8 +4026,54 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const svuint8_t qx1r = svld1rq_u8(svptrue_b8(), x1->qs);
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// 4-bit -> 8-bit
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const svint8_t qx0 = svreinterpret_s8_u8(svlsr_n_u8_m(ptruel, svand_n_u8_m(ptrueh, qx0r, 0x0F), 0x04));
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const svint8_t qx1 = svreinterpret_s8_u8(svlsr_n_u8_m(ptruel, svand_n_u8_m(ptrueh, qx1r, 0x0F), 0x04));
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const svint8_t qx0l = svreinterpret_s8_u8(svand_n_u8_m(svptrue_b8(), qx0r, 0x0F));
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const svint8_t qx0h = svreinterpret_s8_u8(svlsr_n_u8_m(svptrue_b8(), qx0r, 0x04));
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const svint8_t qx1l = svreinterpret_s8_u8(svand_n_u8_m(svptrue_b8(), qx1r, 0x0F));
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const svint8_t qx1h = svreinterpret_s8_u8(svlsr_n_u8_m(svptrue_b8(), qx1r, 0x04));
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// sub 8
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const svint8_t qx0ls = svsub_n_s8_x(svptrue_b8(), qx0h, 8);
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const svint8_t qx0hs = svsub_n_s8_x(svptrue_b8(), qx0l, 8);
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const svint8_t qx1ls = svsub_n_s8_x(svptrue_b8(), qx1h, 8);
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const svint8_t qx1hs = svsub_n_s8_x(svptrue_b8(), qx1l, 8);
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// load y
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const svint8_t qy0h = svld1_s8(svptrue_b8(), y0->qs);
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const svint8_t qy0l = svld1_s8(svptrue_b8(), y0->qs + 16);
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const svint8_t qy1h = svld1_s8(svptrue_b8(), y1->qs);
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const svint8_t qy1l = svld1_s8(svptrue_b8(), y1->qs + 16);
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// dot product
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sumv0 = svmla_n_f32_x(ph4, sumv0, svcvt_f32_s32_x(ph4, svadd_x(ph4,
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svdot_s32(svdup_n_s32(0), qx0ls, qy0l),
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svdot_s32(svdup_n_s32(0), qx0hs, qy0h))), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(ph4, sumv1, svcvt_f32_s32_x(ph4, svadd_x(ph4,
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svdot_s32(svdup_n_s32(0), qx1ls, qy1l),
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svdot_s32(svdup_n_s32(0), qx1hs, qy1h))), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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} break;
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case 256:
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{
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// predicate for activating higher lanes for 16 int8 elements
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const svbool_t ph16 = svptrue_pat_b8(SV_VL16);
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// predicate for activating lower lanes for 16 int8 elements
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const svbool_t pl16 = svnot_b_z(svptrue_b8(), ph16);
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for (; ib + 1 < nb; ib += 2) {
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const block_q4_0 * restrict x0 = &x[ib + 0];
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const block_q4_0 * restrict x1 = &x[ib + 1];
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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// load x
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const svuint8_t qx0r = svld1rq_u8(svptrue_b8(), x0->qs);
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const svuint8_t qx1r = svld1rq_u8(svptrue_b8(), x1->qs);
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// 4-bit -> 8-bit
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const svint8_t qx0 = svreinterpret_s8_u8(svlsr_n_u8_m(pl16, svand_n_u8_m(ph16, qx0r, 0x0F), 0x04));
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const svint8_t qx1 = svreinterpret_s8_u8(svlsr_n_u8_m(pl16, svand_n_u8_m(ph16, qx1r, 0x0F), 0x04));
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// sub 8
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const svint8_t qx0s = svsub_n_s8_x(svptrue_b8(), qx0, 8);
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@ -4033,12 +4084,60 @@ void ggml_vec_dot_q4_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const svint8_t qy1 = svld1_s8(svptrue_b8(), y1->qs);
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// dot product
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sumv0 = svmla_n_f32_x(svptrue_b32(), sumv0, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx0s, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(svptrue_b32(), sumv1, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx1s, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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sumv0 = svmla_n_f32_x(svptrue_b32(), sumv0, svcvt_f32_s32_x(svptrue_b32(),
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svdot_s32(svdup_n_s32(0), qx0s, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(svptrue_b32(), sumv1, svcvt_f32_s32_x(svptrue_b32(),
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svdot_s32(svdup_n_s32(0), qx1s, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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} break;
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case 512:
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{
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// predicate for activating higher lanes for 32 int8 elements
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const svbool_t ph32 = svptrue_pat_b8(SV_VL32);
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// predicate for activating higher lanes for 16 int8 elements
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const svbool_t ph16 = svptrue_pat_b8(SV_VL16);
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// predicate for activating lower lanes for 16 int8 elements from first 32 int8 activated lanes
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const svbool_t pl16 = svnot_b_z(ph32, ph16);
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for (; ib + 1 < nb; ib += 2) {
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const block_q4_0 * restrict x0 = &x[ib + 0];
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const block_q4_0 * restrict x1 = &x[ib + 1];
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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// load x
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const svuint8_t qx0r = svld1rq_u8(ph32, x0->qs);
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const svuint8_t qx1r = svld1rq_u8(ph32, x1->qs);
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// 4-bit -> 8-bit
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const svint8_t qx0 = svreinterpret_s8_u8(svlsr_n_u8_m(pl16, svand_n_u8_m(ph16, qx0r, 0x0F), 0x04));
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const svint8_t qx1 = svreinterpret_s8_u8(svlsr_n_u8_m(pl16, svand_n_u8_m(ph16, qx1r, 0x0F), 0x04));
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// sub 8
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const svint8_t qx0s = svsub_n_s8_x(ph32, qx0, 8);
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const svint8_t qx1s = svsub_n_s8_x(ph32, qx1, 8);
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// load y
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const svint8_t qy0 = svld1_s8(ph32, y0->qs);
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const svint8_t qy1 = svld1_s8(ph32, y1->qs);
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// dot product
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sumv0 = svmla_n_f32_x(ph32, sumv0, svcvt_f32_s32_x(ph32,
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svdot_s32(svdup_n_s32(0), qx0s, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(ph32, sumv1, svcvt_f32_s32_x(ph32,
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svdot_s32(svdup_n_s32(0), qx1s, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(ph32, svadd_f32_x(ph32, sumv0, sumv1));
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} break;
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default:
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assert(false && "Unsupported vector length");
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break;
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}
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#elif defined(__ARM_NEON)
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float32x4_t sumv0 = vdupq_n_f32(0.0f);
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float32x4_t sumv1 = vdupq_n_f32(0.0f);
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@ -5488,10 +5587,50 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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float sumf = 0;
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#if defined(__ARM_FEATURE_SVE)
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if (ggml_sve_cnt_b == QK8_0) {
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svfloat32_t sumv0 = svdup_n_f32(0.0f);
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svfloat32_t sumv1 = svdup_n_f32(0.0f);
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const int vector_length = ggml_sve_cnt_b*8;
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//VLA Implemenation for SVE
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switch (vector_length) {
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case 128:
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{
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// predicate for activating lanes for 16 Int8 elements
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const svbool_t ph16 = svptrue_pat_b8 (SV_VL16);
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const svbool_t pl16 = svptrue_pat_b32(SV_VL4);
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for (; ib + 1 < nb; ib += 2) {
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const block_q8_0 * restrict x0 = &x[ib + 0];
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const block_q8_0 * restrict x1 = &x[ib + 1];
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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// load x
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const svint8_t qx0_0 = svld1_s8(ph16, x0->qs);
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const svint8_t qx0_1 = svld1_s8(ph16, x0->qs+16);
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const svint8_t qx1_0 = svld1_s8(ph16, x1->qs);
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const svint8_t qx1_1 = svld1_s8(ph16, x1->qs+16);
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// load y
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const svint8_t qy0_0 = svld1_s8(ph16, y0->qs);
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const svint8_t qy0_1 = svld1_s8(ph16, y0->qs+16);
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const svint8_t qy1_0 = svld1_s8(ph16, y1->qs);
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const svint8_t qy1_1 = svld1_s8(ph16, y1->qs+16);
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sumv0 = svmla_n_f32_x(pl16, sumv0, svcvt_f32_s32_x(pl16, svadd_x(pl16,
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svdot_s32(svdup_n_s32(0), qx0_0, qy0_0),
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svdot_s32(svdup_n_s32(0), qx0_1, qy0_1))), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(pl16, sumv1, svcvt_f32_s32_x(pl16, svadd_x(pl16,
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svdot_s32(svdup_n_s32(0), qx1_0, qy1_0),
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svdot_s32(svdup_n_s32(0), qx1_1, qy1_1))), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(pl16, svadd_f32_x(pl16, sumv0, sumv1));
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} break;
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case 256:
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{
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//printf("sve256");
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for (; ib + 1 < nb; ib += 2) {
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const block_q8_0 * restrict x0 = &x[ib + 0];
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const block_q8_0 * restrict x1 = &x[ib + 1];
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@ -5506,11 +5645,66 @@ void ggml_vec_dot_q8_0_q8_0(int n, float * restrict s, size_t bs, const void * r
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const svint8_t qy0 = svld1_s8(svptrue_b8(), y0->qs);
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const svint8_t qy1 = svld1_s8(svptrue_b8(), y1->qs);
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sumv0 = svmla_n_f32_x(svptrue_b32(), sumv0, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx0, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(svptrue_b32(), sumv1, svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx1, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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sumv0 = svmla_n_f32_x(svptrue_b32(), sumv0, svcvt_f32_s32_x(svptrue_b32(),
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svdot_s32(svdup_n_s32(0), qx0, qy0)), GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d));
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sumv1 = svmla_n_f32_x(svptrue_b32(), sumv1, svcvt_f32_s32_x(svptrue_b32(),
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svdot_s32(svdup_n_s32(0), qx1, qy1)), GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d));
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}
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sumf = svaddv_f32(svptrue_b32(), svadd_f32_x(svptrue_b32(), sumv0, sumv1));
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} break;
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case 512:
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{
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// predicate for activating high 256 bit
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const svbool_t ph32 = svptrue_pat_b8(SV_VL32);
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// predicate for activating low 256 bit
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const svbool_t pl32 = svnot_b_z(svptrue_b8(), ph32);
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// predicate for activating high lanes for 8 float32 elements
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const svbool_t ph8 = svptrue_pat_b32(SV_VL8);
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// predicate for activating low lanes for 8 float32 elements
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const svbool_t pl8 = svnot_b_z(svptrue_b32(), ph8);
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svfloat32_t sumv00 = svdup_n_f32(0.0f);
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for (; ib + 1 < nb; ib += 2) {
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const block_q8_0 * restrict x0 = &x[ib + 0];
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const block_q8_0 * restrict x1 = &x[ib + 1];
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const block_q8_0 * restrict y0 = &y[ib + 0];
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const block_q8_0 * restrict y1 = &y[ib + 1];
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//load 32 int8_t in first half of vector and put another 32 int8_t in second vector lower bits
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// and add them to make one 64 element vector
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// load x
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const svint8_t qx_32 = svld1_s8(ph32, x0->qs);
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svint8_t qx_64 = svld1_s8(pl32, x0->qs + 2);
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qx_64 = svadd_s8_x(svptrue_b8(), qx_32, qx_64);
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// load y
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const svint8_t qy_32 = svld1_s8(ph32, y0->qs);
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svint8_t qy_64 = svld1_s8(pl32, y0->qs + 2);
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qy_64 = svadd_s8_x(svptrue_b8(), qy_32, qy_64);
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// scale creation
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const float32_t deq1 = GGML_FP16_TO_FP32(x0->d)*GGML_FP16_TO_FP32(y0->d);
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const float32_t deq2 = GGML_FP16_TO_FP32(x1->d)*GGML_FP16_TO_FP32(y1->d);
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// duplicate deq1 in first half of vector and deq2 in second half of vector
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const svfloat32_t temp = svdup_f32_m(svdup_f32_z(ph8, deq1), pl8, deq2);
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const svfloat32_t sumvt = svcvt_f32_s32_x(svptrue_b32(), svdot_s32(svdup_n_s32(0), qx_64, qy_64));
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sumv00 = svmla_f32_m(svptrue_b32(), sumv00, sumvt, temp);
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}
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sumf = svaddv_f32(svptrue_b32(), sumv00);
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break;
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}
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default:
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assert(false && "Unsupported vector length");
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break;
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}
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#elif defined(__ARM_NEON)
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float32x4_t sumv0 = vdupq_n_f32(0.0f);
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