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https://github.com/ggerganov/llama.cpp.git
synced 2024-12-24 13:28:50 +01:00
metal : support bcast add & dup & cont op (#2323)
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commit
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12
ggml-metal.m
12
ggml-metal.m
@ -42,6 +42,7 @@ struct ggml_metal_context {
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id<MTLComputePipelineState> pipeline_##name
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GGML_METAL_DECL_KERNEL(add);
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GGML_METAL_DECL_KERNEL(add_row); // TODO: avoid this extra kernel, instead extend the "add" kernel to support broadcast
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GGML_METAL_DECL_KERNEL(mul);
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GGML_METAL_DECL_KERNEL(mul_row); // TODO: avoid this extra kernel, instead extend the "mul" kernel to support broadcast
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GGML_METAL_DECL_KERNEL(scale);
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@ -157,6 +158,7 @@ struct ggml_metal_context * ggml_metal_init(int n_cb) {
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fprintf(stderr, "%s: loaded %-32s %16p\n", __func__, "kernel_"#name, (void *) ctx->pipeline_##name);
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GGML_METAL_ADD_KERNEL(add);
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GGML_METAL_ADD_KERNEL(add_row);
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GGML_METAL_ADD_KERNEL(mul);
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GGML_METAL_ADD_KERNEL(mul_row);
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GGML_METAL_ADD_KERNEL(scale);
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@ -464,10 +466,16 @@ void ggml_metal_graph_compute(
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encoder = [command_buffer computeCommandEncoder];
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}
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[encoder setComputePipelineState:ctx->pipeline_add];
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if (ggml_nelements(src1) == ne10) {
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// src1 is a row
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[encoder setComputePipelineState:ctx->pipeline_add_row];
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} else {
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[encoder setComputePipelineState:ctx->pipeline_add];
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}
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[encoder setBuffer:id_src0 offset:offs_src0 atIndex:0];
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[encoder setBuffer:id_src1 offset:offs_src1 atIndex:1];
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[encoder setBuffer:id_dst offset:offs_dst atIndex:2];
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[encoder setBytes:&ne00 length:sizeof(ne00) atIndex:3];
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const int64_t n = ggml_nelements(dst);
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@ -919,7 +927,9 @@ void ggml_metal_graph_compute(
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[encoder dispatchThreadgroups:MTLSizeMake(ne01, ne02, ne03) threadsPerThreadgroup:MTLSizeMake(1, 1, 1)];
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} break;
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case GGML_OP_DUP:
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case GGML_OP_CPY:
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case GGML_OP_CONT:
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{
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if (encoder == nil) {
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encoder = [command_buffer computeCommandEncoder];
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@ -67,6 +67,17 @@ kernel void kernel_add(
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dst[tpig] = src0[tpig] + src1[tpig];
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}
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// assumption: src1 is a row
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// broadcast src1 into src0
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kernel void kernel_add_row(
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device const float * src0,
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device const float * src1,
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device float * dst,
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constant int64_t & ne00,
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uint tpig[[thread_position_in_grid]]) {
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dst[tpig] = src0[tpig] + src1[tpig % ne00];
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}
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kernel void kernel_mul(
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device const float * src0,
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device const float * src1,
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