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cuda : optimize argmax (#10441)
* cuda : optimize argmax * remove unused parameter ggml-ci * fixup : use full warps ggml-ci * Apply suggestions from code review Co-authored-by: Johannes Gäßler <johannesg@5d6.de> * fix ub * ggml : check ne00 <= INT32_MAX in argmax and argsort --------- Co-authored-by: Johannes Gäßler <johannesg@5d6.de>
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@ -1,57 +1,69 @@
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#include "common.cuh"
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#include "argmax.cuh"
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#include "sum.cuh"
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#include <algorithm>
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#include <cstdint>
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static __global__ void argmax_f32(
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const float * x, int32_t * dst, const int64_t ncols, const int64_t nrows) {
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#include "argmax.cuh"
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#include "common.cuh"
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#include "sum.cuh"
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int argmax_thread = 0;
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const int64_t row0 = (int64_t)blockIdx.x*WARP_SIZE;
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static __global__ void argmax_f32(const float * __restrict__ x, int32_t * __restrict__ dst, const int64_t ncols) {
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const int64_t row = blockIdx.x;
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#pragma unroll
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for (int64_t row1 = 0; row1 < WARP_SIZE; ++row1) {
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const int64_t row = row0 + row1;
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float maxval = -FLT_MAX;
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int argmax = -1;
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const float * rowx = x + row * ncols;
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if (row >= nrows) {
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break;
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for (int32_t col = threadIdx.x; col < ncols; col += blockDim.x) {
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const float val = rowx[col];
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if (val > maxval) {
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maxval = val;
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argmax = col;
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}
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float maxval = -FLT_MAX;
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int argmax = -1;
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for (int32_t col = threadIdx.x; col < ncols; col += WARP_SIZE) {
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const float val = x[row*ncols + col];
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const int bigger = val > maxval;
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const int not_bigger = bigger ^ 0x00000001;
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maxval = maxval*not_bigger + val*bigger;
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argmax = argmax*not_bigger + col*bigger;
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}
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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const float val = __shfl_xor_sync(0xFFFFFFFF, maxval, mask, WARP_SIZE);
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const int col = __shfl_xor_sync(0xFFFFFFFF, argmax, mask, WARP_SIZE);
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const int bigger = val > maxval;
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const int not_bigger = bigger ^ 0x00000001;
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maxval = maxval*not_bigger + val*bigger;
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argmax = argmax*not_bigger + col*bigger;
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}
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const int store = row1 == threadIdx.x;
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argmax_thread += store*argmax;
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}
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const int row = row0 + threadIdx.x;
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if (row >= nrows) {
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return;
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1) {
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const float val = __shfl_xor_sync(0xFFFFFFFF, maxval, offset, WARP_SIZE);
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const int col = __shfl_xor_sync(0xFFFFFFFF, argmax, offset, WARP_SIZE);
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if (val > maxval) {
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maxval = val;
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argmax = col;
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}
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}
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dst[row] = argmax_thread;
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const int n_warps = blockDim.x / WARP_SIZE;
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const int lane_id = threadIdx.x % WARP_SIZE;
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const int warp_id = threadIdx.x / WARP_SIZE;
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if (n_warps > 1) {
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constexpr int max_warps = 1024 / WARP_SIZE;
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__shared__ float shared_maxval[max_warps];
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__shared__ int shared_argmax[max_warps];
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if (lane_id == 0) {
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shared_maxval[warp_id] = maxval;
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shared_argmax[warp_id] = argmax;
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}
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__syncthreads();
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if (warp_id == 0) {
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if (lane_id < n_warps) {
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maxval = shared_maxval[lane_id];
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argmax = shared_argmax[lane_id];
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}
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#pragma unroll
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for (int offset = 16; offset > 0; offset >>= 1) {
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const float val = __shfl_xor_sync(0xFFFFFFFF, maxval, offset, WARP_SIZE);
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const int col = __shfl_xor_sync(0xFFFFFFFF, argmax, offset, WARP_SIZE);
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if (val > maxval) {
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maxval = val;
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argmax = col;
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}
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}
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}
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}
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if (warp_id == 0 && lane_id == 0) {
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dst[row] = argmax;
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}
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}
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void ggml_cuda_argmax(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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@ -70,10 +82,10 @@ void ggml_cuda_argmax(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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cudaStream_t stream = ctx.stream();
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const int64_t num_blocks = (nrows + WARP_SIZE - 1) / WARP_SIZE;
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const dim3 blocks_dim(WARP_SIZE, 1, 1);
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const int64_t num_blocks = nrows;
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const int64_t num_threads = std::min<int64_t>(1024, (ne00 + WARP_SIZE - 1) / WARP_SIZE * WARP_SIZE);
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const dim3 blocks_dim(num_threads, 1, 1);
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const dim3 blocks_num(num_blocks, 1, 1);
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argmax_f32<<<blocks_num, blocks_dim, 0, stream>>>(src0_d, dst_d, ne00, nrows);
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argmax_f32<<<blocks_num, blocks_dim, 0, stream>>>(src0_d, dst_d, ne00);
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}
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@ -180,8 +180,8 @@ static __device__ __forceinline__ int warp_reduce_sum(int x) {
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return __reduce_add_sync(0xffffffff, x);
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#else
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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x += __shfl_xor_sync(0xffffffff, x, mask, 32);
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for (int offset = 16; offset > 0; offset >>= 1) {
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x += __shfl_xor_sync(0xffffffff, x, offset, 32);
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}
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return x;
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#endif // !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= CC_AMPERE
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@ -189,17 +189,17 @@ static __device__ __forceinline__ int warp_reduce_sum(int x) {
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static __device__ __forceinline__ float warp_reduce_sum(float x) {
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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x += __shfl_xor_sync(0xffffffff, x, mask, 32);
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for (int offset = 16; offset > 0; offset >>= 1) {
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x += __shfl_xor_sync(0xffffffff, x, offset, 32);
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}
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return x;
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}
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static __device__ __forceinline__ float2 warp_reduce_sum(float2 a) {
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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a.x += __shfl_xor_sync(0xffffffff, a.x, mask, 32);
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a.y += __shfl_xor_sync(0xffffffff, a.y, mask, 32);
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for (int offset = 16; offset > 0; offset >>= 1) {
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a.x += __shfl_xor_sync(0xffffffff, a.x, offset, 32);
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a.y += __shfl_xor_sync(0xffffffff, a.y, offset, 32);
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}
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return a;
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}
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@ -209,16 +209,16 @@ static __device__ __forceinline__ half2 warp_reduce_sum(half2 a) {
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#if defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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const half2 a_other = __shfl_xor_sync(0xffffffff, a, mask, 32);
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for (int offset = 16; offset > 0; offset >>= 1) {
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const half2 a_other = __shfl_xor_sync(0xffffffff, a, offset, 32);
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reinterpret_cast<half&>(a.x) += __low2half(a_other);
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reinterpret_cast<half&>(a.y) += __high2half(a_other);
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}
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return a;
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#else
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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a = __hadd2(a, __shfl_xor_sync(0xffffffff, a, mask, 32));
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for (int offset = 16; offset > 0; offset >>= 1) {
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a = __hadd2(a, __shfl_xor_sync(0xffffffff, a, offset, 32));
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}
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return a;
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#endif // defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)
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@ -231,8 +231,8 @@ static __device__ __forceinline__ half2 warp_reduce_sum(half2 a) {
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static __device__ __forceinline__ float warp_reduce_max(float x) {
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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x = fmaxf(x, __shfl_xor_sync(0xffffffff, x, mask, 32));
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for (int offset = 16; offset > 0; offset >>= 1) {
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x = fmaxf(x, __shfl_xor_sync(0xffffffff, x, offset, 32));
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}
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return x;
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}
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@ -275,8 +275,8 @@ static __device__ __forceinline__ half2 ggml_cuda_hmax2(const half2 a, const hal
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static __device__ __forceinline__ half2 warp_reduce_max(half2 x) {
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#if !(defined(GGML_USE_HIP) && defined(__HIP_PLATFORM_AMD__)) && __CUDA_ARCH__ >= CC_PASCAL
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#pragma unroll
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for (int mask = 16; mask > 0; mask >>= 1) {
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x = ggml_cuda_hmax2(x, __shfl_xor_sync(0xffffffff, x, mask, 32));
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for (int offset = 16; offset > 0; offset >>= 1) {
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x = ggml_cuda_hmax2(x, __shfl_xor_sync(0xffffffff, x, offset, 32));
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}
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return x;
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#else
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@ -69,8 +69,8 @@ static __global__ void quantize_mmq_q8_1(
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// Exchange max. abs. value between vals_per_scale/4 threads.
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#pragma unroll
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for (int mask = vals_per_scale/8; mask > 0; mask >>= 1) {
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amax = fmaxf(amax, __shfl_xor_sync(0xFFFFFFFF, amax, mask, WARP_SIZE));
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for (int offset = vals_per_scale/8; offset > 0; offset >>= 1) {
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amax = fmaxf(amax, __shfl_xor_sync(0xFFFFFFFF, amax, offset, WARP_SIZE));
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}
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float sum;
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@ -79,8 +79,8 @@ static __global__ void quantize_mmq_q8_1(
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// Exchange calculate sum across vals_per_sum/4 threads.
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#pragma unroll
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for (int mask = vals_per_sum/8; mask > 0; mask >>= 1) {
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sum += __shfl_xor_sync(0xFFFFFFFF, sum, mask, WARP_SIZE);
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for (int offset = vals_per_sum/8; offset > 0; offset >>= 1) {
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sum += __shfl_xor_sync(0xFFFFFFFF, sum, offset, WARP_SIZE);
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}
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}
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@ -2255,6 +2255,7 @@ struct ggml_tensor * ggml_argmax(
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struct ggml_context * ctx,
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struct ggml_tensor * a) {
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GGML_ASSERT(ggml_is_matrix(a));
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GGML_ASSERT(a->ne[0] <= INT32_MAX);
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struct ggml_tensor * result = ggml_new_tensor_1d(ctx, GGML_TYPE_I32, a->ne[1]);
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@ -4138,6 +4139,7 @@ struct ggml_tensor * ggml_argsort(
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struct ggml_context * ctx,
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struct ggml_tensor * a,
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enum ggml_sort_order order) {
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GGML_ASSERT(a->ne[0] <= INT32_MAX);
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struct ggml_tensor * result = ggml_new_tensor(ctx, GGML_TYPE_I32, GGML_MAX_DIMS, a->ne);
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ggml_set_op_params_i32(result, 0, (int32_t) order);
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@ -1154,6 +1154,26 @@ struct test_argmax : public test_case {
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return out;
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}
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void initialize_tensors(ggml_context * ctx) override {
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std::random_device rd;
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std::default_random_engine rng(rd());
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for (ggml_tensor * t = ggml_get_first_tensor(ctx); t != NULL; t = ggml_get_next_tensor(ctx, t)) {
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if (t->type == GGML_TYPE_F32) {
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// initialize with unique values to avoid ties
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for (int64_t r = 0; r < ggml_nrows(t); r++) {
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std::vector<float> data(t->ne[0]);
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for (int i = 0; i < t->ne[0]; i++) {
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data[i] = i;
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}
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std::shuffle(data.begin(), data.end(), rng);
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ggml_backend_tensor_set(t, data.data(), r * t->nb[1], t->ne[0] * sizeof(float));
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}
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} else {
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init_tensor_uniform(t);
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}
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}
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}
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double max_nmse_err() override {
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return 0.0;
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}
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@ -3440,6 +3460,11 @@ static std::vector<std::unique_ptr<test_case>> make_test_cases_eval() {
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test_cases.emplace_back(new test_conv_transpose_1d({2,1,1,1}, {3,1,1,1}, 1, 0, 1));
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test_cases.emplace_back(new test_argmax());
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {32, 1, 1, 1}));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {100, 10, 1, 1}));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {1024, 10, 1, 1}));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {2000, 10, 1, 1}));
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test_cases.emplace_back(new test_count_equal());
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for (int ne3 : {1, 3}) { // CUDA backward pass only supports ne3 == 1
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@ -3830,6 +3855,10 @@ static std::vector<std::unique_ptr<test_case>> make_test_cases_perf() {
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test_cases.emplace_back(new test_soft_max(GGML_TYPE_F32, {64, 64, 20, 1}, false, 1.0f, 0.0f));
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test_cases.emplace_back(new test_soft_max(GGML_TYPE_F32, {77, 64, 20, 1}, false, 1.0f, 0.0f));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {32, 10, 1, 1}));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {1024, 10, 1, 1}));
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test_cases.emplace_back(new test_argmax(GGML_TYPE_F32, {32000, 512, 1, 1}));
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for (int bs : {1, 512}) {
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for (ggml_type type_a : all_types) {
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for (ggml_type type_b : {GGML_TYPE_F32}) {
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