mirror of
https://github.com/ggerganov/llama.cpp.git
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9c67c2773d
* ggml : add ggml_flash_attn_ext API * ggml : fix GQA support in ggml_flash_attn_ext * ggml : online attention (CPU) * metal : initial implementation * metal : f16 precision * metal : reduce branches * metal : specialize for head size * wip : 8 rows per simd group * wip : 4 rows per simd group * wip : template for rows per warp * metal : parallelize across KV size * metal : parallel reduce across heads * metal : efficient flash_attn_f16 implementation * metal : avoid redundant loads of the attention * metal : scale and mask in matrix form * metal : fix comment * llama : avoid ggml_cast, use F32 query * metal : add parallel reduce version (disabled) * metal : move output into local memory + optimize - the result from each simdgroup now stays in the registers - significantly reduced SRAM usage - more efficient skipping of -INF blocks - avoid simdgroup barrier in hot loop - add comments * metal : add tests, fix scaling, support C > 32 * metal : improve precision * ggml : fix f16 mad * metal : minor * metal : support Q > 8 * tests : add ATTN tests * metal : disable buffer allocation logs * tests : more * metal : faster inner loop for C == 32 * metal : fix array initialization * tests : ifdef * ggml : switch to padded F16 mask for ggml_soft_max, ggml_flash_attn_ext * ggml : fix ggml_soft_max mask requirement * cuda : fix soft_max to use correct mask size * cuda : add flash_attn kernel (wip) * metal : optimize softmax for C > 32 * metal : optimize softmax * tests : minor fix * cuda : avoid zeroing fragments * tests : update dims * cuda : fix __hisinf() result check * cuda : avoid warp_reduce for smax * cuda : use int instead of int64_t Noticeably improves performance (thanks to Johannes) * cuda : make loops use the same loop values Thanks Johannes again for the tip * cuda : unroll some of the loops * cuda : avoid __hisinf branches * cuda : use half2 in softmax * cuda : switch to 1 warp for bs > 16 * cuda : speed-up reduce part of the kernel * cuda : unroll Q*K^T loop * cuda : fix -INF block check * cuda : simplify softmax * cuda : fix matrix names * cuda : minor * llama : adapt to F16 KQ_pos * llama : adapt new models to F16 KQ_mask * ggml : fix F16 store (ARM NEON) * llama : fix type of KQ_mask and KQ_pos * ggml : fix CPU soft_max * tests : add hs=256 * cuda : fix build * metal : improve perf via smaller int registers * cuda : adapt soft_max to F16 mask and pos * CUDA: faster FlashAttention, kernel for bs == 1 * 16 cols for Phi-2 * no vec for hs, no hs==256 ncols==32 for Volta * adjust kernel selection logic * 4 warps, 256 stride for all D * no ncols == 64 * Multiple parallel blocks for batch size 1 * fix compile warnings * fix excessive KQ_b loads * fix cmake build * fix KV cache padding, NaN from INFINITY (#6438) * llama : flash_attn cparam + fix defrag * server: support flash_attn param * server: bench: enable flash_attn param * CUDA: refactor host code, dyn. par. blocks * fix flash_attn_vec_f16 race condition * flush softmax exp below threshold to 0 * store temp KQ in registers * Calculate KQ as FP32 if KQV has GGML_PREC_F32 * Add __hgt2_mask implementation for CUDA 11 * fix KQ FP32 precision fpr parallel_blocks > 1 * llama-bench : add -fa,--flash-attn arg * metal : add BS=1 kernel for flash attention (#6508) * metal : add BS=1 kernel for flash attention (wip) * metal : support more than 1 warps * metal : opts * metal : opt * metal : switch to parallel reduce * metal : reduce registers * metal : simplify * metal : initial FA vec kernel * metal : use F32 attention accumulators * batched-bench : add fattn arg * llama : simplify llama_build_kv_store ggml-ci * llama : adapt build_olmo to changes * ggml : fix arm fp16 store on windows * metal : clean-up * metal : clean-up kernel code * metal : minor * tests : remove benchmarks ggml-ci * ggml : fix avx512 const correctness ggml-ci * ggml : fix soft_max with bias on CPU ggml-ci * common : print --flash-attn in help * ggml : fix num dimensions in ggml_flash_attn_ext * llama : force disable flash attention for incompatible models * ggml : ggml_soft_max support F16/F32 mask/pos ggml-ci * cuda : uint -> uint32_t * cuda : "constexpr dim3" -> "const dim3" ggml-ci * cuda : try to fix __hgt2_mask ggml-ci * ggml : add TODO's for F16/F32 mask/pos support in other backends * llama : replace bool need_kq_pos with use_alibi * llama : prep ALiBi support for BERT models ggml-ci * llama : fix n_batch requirements ggml-ci * cont * server : add help for --flash-attn arg * llama : disable FA for AMD * tests : remove TMP_ATTN_BENCH ggml-ci * llama : support save/load state with FA enabled ggml-ci * ci : add CUDA save-load-state tests ggml-ci * llama : llama_kv_cache_clear zeroes data + fix save-load seq ggml-ci * llama : fix copy-paste errors, add TODO * llama : disallow incompatible states * llama : update llama_state_get_size after v_trans field * metal : remove tmp log * llama : add static reminder for llama_state_get_size * metal : fix max nsg ggml-ci * ci : fix arg order ggml-ci --------- Co-authored-by: Johannes Gäßler <johannesg@5d6.de> Co-authored-by: Pierrick HYMBERT <pierrick.hymbert@gmail.com>
228 lines
8.3 KiB
Plaintext
228 lines
8.3 KiB
Plaintext
#include "softmax.cuh"
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template <typename T>
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static __device__ __forceinline__ float t2f32(T val) {
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return (float) val;
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}
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template <>
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__device__ float __forceinline__ t2f32<half>(half val) {
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return __half2float(val);
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}
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template <bool vals_smem, int ncols_template, int block_size_template, typename T>
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static __global__ void soft_max_f32(const float * x, const T * mask, const T * pos, float * dst, const int ncols_par, const int nrows_y, const float scale, const float max_bias, const float m0, const float m1, uint32_t n_head_log2) {
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const int ncols = ncols_template == 0 ? ncols_par : ncols_template;
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const int tid = threadIdx.x;
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const int rowx = blockIdx.x;
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const int rowy = rowx % nrows_y; // broadcast the mask in the row dimension
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const int block_size = block_size_template == 0 ? blockDim.x : block_size_template;
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const int warp_id = threadIdx.x / WARP_SIZE;
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const int lane_id = threadIdx.x % WARP_SIZE;
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float slope = 0.0f;
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// ALiBi
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if (max_bias > 0.0f) {
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const int h = rowx/nrows_y; // head index
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const float base = h < n_head_log2 ? m0 : m1;
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const int exp = h < n_head_log2 ? h + 1 : 2*(h - n_head_log2) + 1;
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slope = powf(base, exp);
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}
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extern __shared__ float data_soft_max_f32[];
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float * buf_iw = data_soft_max_f32; // shared memory buffer for inter-warp communication
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// shared memory buffer to cache values between iterations:
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float * vals = vals_smem ? buf_iw + WARP_SIZE : dst + (int64_t)rowx*ncols;
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float max_val = -INFINITY;
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#pragma unroll
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for (int col0 = 0; col0 < ncols; col0 += block_size) {
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const int col = col0 + tid;
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if (ncols_template == 0 && col >= ncols) {
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break;
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}
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const int64_t ix = (int64_t)rowx*ncols + col;
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const int64_t iy = (int64_t)rowy*ncols + col;
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const float val = x[ix]*scale + (mask ? t2f32(mask[iy]) : 0.0f) + (pos ? slope*t2f32(pos[col]) : 0.0f);
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vals[col] = val;
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max_val = max(max_val, val);
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}
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// find the max value in the block
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max_val = warp_reduce_max(max_val);
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if (block_size > WARP_SIZE) {
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if (warp_id == 0) {
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buf_iw[lane_id] = -INFINITY;
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}
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__syncthreads();
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if (lane_id == 0) {
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buf_iw[warp_id] = max_val;
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}
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__syncthreads();
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max_val = buf_iw[lane_id];
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max_val = warp_reduce_max(max_val);
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}
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float tmp = 0.0f; // partial sum
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#pragma unroll
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for (int col0 = 0; col0 < ncols; col0 += block_size) {
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const int col = col0 + tid;
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if (ncols_template == 0 && col >= ncols) {
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break;
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}
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const float val = expf(vals[col] - max_val);
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tmp += val;
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vals[col] = val;
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}
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// find the sum of exps in the block
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tmp = warp_reduce_sum(tmp);
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if (block_size > WARP_SIZE) {
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__syncthreads();
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if (warp_id == 0) {
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buf_iw[lane_id] = 0.0f;
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}
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__syncthreads();
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if (lane_id == 0) {
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buf_iw[warp_id] = tmp;
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}
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__syncthreads();
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tmp = buf_iw[lane_id];
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tmp = warp_reduce_sum(tmp);
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}
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const float inv_sum = 1.0f / tmp;
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#pragma unroll
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for (int col0 = 0; col0 < ncols; col0 += block_size) {
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const int col = col0 + tid;
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if (ncols_template == 0 && col >= ncols) {
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return;
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}
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const int64_t idst = (int64_t)rowx*ncols + col;
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dst[idst] = vals[col] * inv_sum;
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}
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}
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template<typename T>
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static void soft_max_f32_cuda(const float * x, const T * mask, const T * pos, float * dst, const int ncols_x, const int nrows_x, const int nrows_y, const float scale, const float max_bias, cudaStream_t stream) {
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int nth = WARP_SIZE;
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while (nth < ncols_x && nth < CUDA_SOFT_MAX_BLOCK_SIZE) nth *= 2;
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const dim3 block_dims(nth, 1, 1);
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const dim3 block_nums(nrows_x, 1, 1);
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const size_t shmem = (GGML_PAD(ncols_x, WARP_SIZE) + WARP_SIZE)*sizeof(float);
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static_assert(CUDA_SOFT_MAX_BLOCK_SIZE == 1024, "These values need to be adjusted.");
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const uint32_t n_head_kv = nrows_x/nrows_y;
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const uint32_t n_head_log2 = 1u << (uint32_t) floorf(log2f((float) n_head_kv));
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const float m0 = powf(2.0f, -(max_bias ) / n_head_log2);
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const float m1 = powf(2.0f, -(max_bias / 2.0f) / n_head_log2);
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if (shmem < ggml_cuda_info().devices[ggml_cuda_get_device()].smpb) {
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switch (ncols_x) {
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case 32:
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soft_max_f32<true, 32, 32><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 64:
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soft_max_f32<true, 64, 64><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 128:
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soft_max_f32<true, 128, 128><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 256:
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soft_max_f32<true, 256, 256><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 512:
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soft_max_f32<true, 512, 512><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 1024:
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soft_max_f32<true, 1024, 1024><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 2048:
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soft_max_f32<true, 2048, 1024><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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case 4096:
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soft_max_f32<true, 4096, 1024><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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default:
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soft_max_f32<true, 0, 0><<<block_nums, block_dims, shmem, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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break;
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}
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} else {
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const size_t shmem_low = WARP_SIZE*sizeof(float);
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soft_max_f32<false, 0, 0><<<block_nums, block_dims, shmem_low, stream>>>(x, mask, pos, dst, ncols_x, nrows_y, scale, max_bias, m0, m1, n_head_log2);
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}
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}
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void ggml_cuda_op_soft_max(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * src0 = dst->src[0];
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const ggml_tensor * src1 = dst->src[1];
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const ggml_tensor * src2 = dst->src[2];
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const float * src0_d = (const float *)src0->data;
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const void * src1_d = src1 ? (const void *)src1->data : nullptr;
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float * dst_d = (float *)dst->data;
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cudaStream_t stream = ctx.stream();
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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GGML_ASSERT(!src1 || src1->type == GGML_TYPE_F16 || src1->type == GGML_TYPE_F32); // src1 contains mask and it is optional
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GGML_ASSERT(!src2 || src2->type == GGML_TYPE_F16 || src2->type == GGML_TYPE_F32); // src2 contains positions and it is optional
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const int64_t ne00 = src0->ne[0];
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const int64_t nrows_x = ggml_nrows(src0);
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const int64_t nrows_y = src0->ne[1];
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float scale = 1.0f;
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float max_bias = 0.0f;
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memcpy(&scale, (float *) dst->op_params + 0, sizeof(float));
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memcpy(&max_bias, (float *) dst->op_params + 1, sizeof(float));
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// positions tensor
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void * src2_d = nullptr;
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const bool use_src2 = src2 != nullptr;
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if (use_src2) {
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src2_d = (void *)src2->data;
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}
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const bool use_f16 = (src1 && src1->type == GGML_TYPE_F16) || (src2 && src2->type == GGML_TYPE_F16);
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if (use_f16) {
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const half * src1_dd = (const half *)src1_d;
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const half * src2_dd = (const half *)src2_d;
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soft_max_f32_cuda(src0_d, src1_dd, src2_dd, dst_d, ne00, nrows_x, nrows_y, scale, max_bias, stream);
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} else {
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const float * src1_dd = (const float *)src1_d;
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const float * src2_dd = (const float *)src2_d;
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soft_max_f32_cuda(src0_d, src1_dd, src2_dd, dst_d, ne00, nrows_x, nrows_y, scale, max_bias, stream);
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}
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}
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