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https://github.com/ggerganov/llama.cpp.git
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750cb3e246
* Renames NVIDIA GPU-architecture flags to avoid name clashes with WinAPI. (e.g. CC_PASCAL, GPU architecture or WinAPI pascal compiler flag?) * Reverts erroneous rename in SYCL-code. * Renames GGML_CUDA_MIN_CC_DP4A to GGML_CUDA_CC_DP4A. * Renames the rest of the compute capability macros for consistency.
46 lines
1.5 KiB
Plaintext
46 lines
1.5 KiB
Plaintext
#if !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11700
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#define USE_CUB
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#endif // !defined(GGML_USE_HIP) && !defined(GGML_USE_MUSA) && CUDART_VERSION >= 11700
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#ifdef USE_CUB
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#include <cub/cub.cuh>
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using namespace cub;
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#endif // USE_CUB
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#include "sumrows.cuh"
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#include "sum.cuh"
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#include <cstdint>
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void sum_f32_cuda(ggml_cuda_pool & pool, const float * x, float * dst, const int64_t ne, cudaStream_t stream) {
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#ifdef USE_CUB
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size_t tmp_size = 0;
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DeviceReduce::Sum(nullptr, tmp_size, x, dst, ne, stream);
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ggml_cuda_pool_alloc<uint8_t> tmp_alloc(pool, tmp_size);
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DeviceReduce::Sum(tmp_alloc.ptr, tmp_size, x, dst, ne, stream);
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#else
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// Use (inefficient) sum_rows implementation as a fallback.
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// For AMD there is rocPRIM which could be used as a drop-in replacement via hipcub but this would require C++11 -> C++14.
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sum_rows_f32_cuda(x, dst, ne, 1, stream);
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GGML_UNUSED(pool);
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#endif // USE_CUB
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}
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void ggml_cuda_op_sum(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * src0 = dst->src[0];
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GGML_ASSERT(src0->type == GGML_TYPE_F32);
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GGML_ASSERT( dst->type == GGML_TYPE_F32);
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GGML_ASSERT(ggml_is_contiguous(src0));
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const float * src0_d = (const float *) src0->data;
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float * dst_d = (float *) dst->data;
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const int64_t ne = ggml_nelements(src0);
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ggml_cuda_pool & pool = ctx.pool();
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cudaStream_t stream = ctx.stream();
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sum_f32_cuda(pool, src0_d, dst_d, ne, stream);
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}
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