mirror of
https://github.com/ggerganov/llama.cpp.git
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a5e47592b6
* cuda : optimize argmax * remove unused parameter ggml-ci * fixup : use full warps ggml-ci * Apply suggestions from code review Co-authored-by: Johannes Gäßler <johannesg@5d6.de> * fix ub * ggml : check ne00 <= INT32_MAX in argmax and argsort --------- Co-authored-by: Johannes Gäßler <johannesg@5d6.de>
170 lines
5.4 KiB
Plaintext
170 lines
5.4 KiB
Plaintext
#include "quantize.cuh"
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#include <cstdint>
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static __global__ void quantize_q8_1(const float * __restrict__ x, void * __restrict__ vy, const int64_t kx, const int64_t kx0_padded) {
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const int64_t ix0 = (int64_t)blockDim.x*blockIdx.x + threadIdx.x;
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if (ix0 >= kx0_padded) {
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return;
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}
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const int64_t ix1 = blockIdx.y;
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const int64_t i_padded = ix1*kx0_padded + ix0;
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block_q8_1 * y = (block_q8_1 *) vy;
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const int64_t ib = i_padded / QK8_1; // block index
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const int64_t iqs = i_padded % QK8_1; // quant index
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const float xi = ix0 < kx ? x[ix1*kx + ix0] : 0.0f;
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float amax = fabsf(xi);
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float sum = xi;
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amax = warp_reduce_max(amax);
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sum = warp_reduce_sum(sum);
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const float d = amax / 127;
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const int8_t q = amax == 0.0f ? 0 : roundf(xi / d);
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y[ib].qs[iqs] = q;
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if (iqs > 0) {
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return;
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}
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reinterpret_cast<half&>(y[ib].ds.x) = d;
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reinterpret_cast<half&>(y[ib].ds.y) = sum;
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}
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template <mmq_q8_1_ds_layout ds_layout>
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static __global__ void quantize_mmq_q8_1(
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const float * __restrict__ x, void * __restrict__ vy, const int64_t kx0, const int64_t kx1, const int64_t kx0_padded) {
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constexpr int vals_per_scale = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 64 : 32;
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constexpr int vals_per_sum = ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6 ? 16 : 32;
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const int64_t ix0 = ((int64_t)blockDim.x*blockIdx.x + threadIdx.x)*4;
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if (ix0 >= kx0_padded) {
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return;
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}
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const float4 * x4 = (const float4 *) x;
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const int64_t ix1 = kx1*blockIdx.z + blockIdx.y;
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block_q8_1_mmq * y = (block_q8_1_mmq *) vy;
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const int64_t ib0 = blockIdx.z*((int64_t)gridDim.y*gridDim.x*blockDim.x/QK8_1); // first block of channel
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const int64_t ib = ib0 + (ix0 / (4*QK8_1))*kx1 + blockIdx.y; // block index in channel
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const int64_t iqs = ix0 % (4*QK8_1); // quant index in block
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// Load 4 floats per thread and calculate max. abs. value between them:
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const float4 xi = ix0 < kx0 ? x4[(ix1*kx0 + ix0)/4] : make_float4(0.0f, 0.0f, 0.0f, 0.0f);
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float amax = fabsf(xi.x);
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amax = fmaxf(amax, fabsf(xi.y));
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amax = fmaxf(amax, fabsf(xi.z));
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amax = fmaxf(amax, fabsf(xi.w));
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// Exchange max. abs. value between vals_per_scale/4 threads.
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#pragma unroll
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for (int offset = vals_per_scale/8; offset > 0; offset >>= 1) {
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amax = fmaxf(amax, __shfl_xor_sync(0xFFFFFFFF, amax, offset, WARP_SIZE));
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}
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float sum;
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if (ds_layout != MMQ_Q8_1_DS_LAYOUT_D4) {
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sum = xi.x + xi.y + xi.z + xi.w;
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// Exchange calculate sum across vals_per_sum/4 threads.
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#pragma unroll
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for (int offset = vals_per_sum/8; offset > 0; offset >>= 1) {
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sum += __shfl_xor_sync(0xFFFFFFFF, sum, offset, WARP_SIZE);
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}
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}
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const float d_inv = 127.0f / amax;
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char4 q;
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q.x = roundf(xi.x*d_inv);
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q.y = roundf(xi.y*d_inv);
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q.z = roundf(xi.z*d_inv);
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q.w = roundf(xi.w*d_inv);
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// Write back 4 int8 values as a single 32 bit value for better memroy bandwidth:
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char4 * yqs4 = (char4 *) y[ib].qs;
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yqs4[iqs/4] = q;
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if (ds_layout == MMQ_Q8_1_DS_LAYOUT_D2S6) {
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if (iqs % 16 != 0 || iqs >= 96) {
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return;
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}
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y[ib].d2s6[2 + iqs/16] = sum;
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if (iqs % 64 != 0) {
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return;
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}
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const float d = 1.0f / d_inv;
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y[ib].d2s6[iqs/64] = d;
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return;
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}
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if (iqs % 32 != 0) {
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return;
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}
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const float d = 1.0f / d_inv;
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if (ds_layout == MMQ_Q8_1_DS_LAYOUT_DS4) {
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y[ib].ds4[iqs/32] = make_half2(d, sum);
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} else {
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y[ib].d4[iqs/32] = d;
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}
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}
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void quantize_row_q8_1_cuda(
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const float * x, void * vy, const int64_t kx0, const int64_t kx1, const int64_t channels,
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const int64_t kx0_padded, const ggml_type type_x, cudaStream_t stream) {
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GGML_ASSERT(kx0_padded % QK8_1 == 0);
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const int64_t block_num_x = (kx0_padded + CUDA_QUANTIZE_BLOCK_SIZE - 1) / CUDA_QUANTIZE_BLOCK_SIZE;
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const dim3 num_blocks(block_num_x, kx1*channels, 1);
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const dim3 block_size(CUDA_QUANTIZE_BLOCK_SIZE, 1, 1);
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quantize_q8_1<<<num_blocks, block_size, 0, stream>>>(x, vy, kx0, kx0_padded);
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GGML_UNUSED(type_x);
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}
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void quantize_mmq_q8_1_cuda(
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const float * x, void * vy, const int64_t kx0, const int64_t kx1, const int64_t channels,
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const int64_t kx0_padded, const ggml_type type_x, cudaStream_t stream) {
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GGML_ASSERT(kx0_padded % (4*QK8_1) == 0);
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const int64_t block_num_x = (kx0_padded + 4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ - 1) / (4*CUDA_QUANTIZE_BLOCK_SIZE_MMQ);
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const dim3 num_blocks(block_num_x, kx1, channels);
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const dim3 block_size(CUDA_QUANTIZE_BLOCK_SIZE_MMQ, 1, 1);
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switch (mmq_get_q8_1_ds_layout(type_x)) {
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case MMQ_Q8_1_DS_LAYOUT_D4:
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quantize_mmq_q8_1<MMQ_Q8_1_DS_LAYOUT_D4>
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<<<num_blocks, block_size, 0, stream>>>(x, vy, kx0, kx1, kx0_padded);
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break;
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case MMQ_Q8_1_DS_LAYOUT_DS4:
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quantize_mmq_q8_1<MMQ_Q8_1_DS_LAYOUT_DS4>
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<<<num_blocks, block_size, 0, stream>>>(x, vy, kx0, kx1, kx0_padded);
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break;
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case MMQ_Q8_1_DS_LAYOUT_D2S6:
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quantize_mmq_q8_1<MMQ_Q8_1_DS_LAYOUT_D2S6>
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<<<num_blocks, block_size, 0, stream>>>(x, vy, kx0, kx1, kx0_padded);
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break;
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default:
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GGML_ABORT("fatal error");
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break;
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}
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}
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